Powerlattice Demonstrates Industry’s First Monolithic IVR Chiplet to Break the AI Power Wall

Powerlattice Demonstrates Industry’s First Monolithic IVR Chiplet to Break the AI Power Wall

Power delivery chiplet tightly couples power and compute to unlock next-generation AI accelerator performance

Powerlattice, the company reimagining power delivery for next-generation AI accelerators, announced the successful demonstration of the industry’s first monolithic integrated voltage regulator (IVR) chiplet under conditions that emulate next-generation AI accelerators. The demonstration shows how the chiplet responds to rapid changes in power demand, addressing a critical challenge as AI pushes beyond the limits of conventional power delivery.

Conventional power delivery forces high electrical current to travel long, resistive paths before reaching the processor, wasting energy and limiting performance. Powerlattice dramatically shortens that path by tightly coupling power and compute. The company’s technology reduces total compute power needs by more than 50%, effectively doubling performance.

“Breaking through the AI power wall requires us to rethink how power reaches the processor,” said Peng Zou, co-founder and CEO of Powerlattice. “By integrating point-of-load power delivery directly into the processor package, we give designers the flexibility to tailor power delivery to their processors, whether using an individual IVR chiplet or a synchronized array. This enables dramatic performance gains that will make IVR chiplets the de facto platform for point-of-load power delivery in data center AI processors.”

Reimagining power for AI

Powerlattice’s monolithic architecture integrates the controller, power transistors and inductors into a single chiplet. Integrating these elements reduces the connections between separate components and is designed to minimize parasitic inductance and resistance. Bringing regulation closer to compute helps stabilize power delivery, reduce energy loss and address the power-related throttling that limits accelerator utilization.

The platform combines PowerMagixTM miniaturized on-die magnetic film inductors with advanced voltage control and a configurable architecture. PowerMagix integrates the inductors directly on the chiplet to support compact, efficient power delivery. In addition, Programmable Power Array (P2ATM) synchronization allows multiple separate IVR chiplets to behave as one unified platform, matching power delivery to an accelerator’s load requirements.

Designers can configure an individual chiplet or a synchronized array to support different AI accelerator designs. This flexibility extends Powerlattice’s approach to delivering power with the consistency, precision and stability needed for greater compute utilization and AI-grade reliability.

Demonstrating next-generation accelerator power demands

As part of the demonstration, Powerlattice’s IVR chiplet supplied power to a high-precision silicon device developed by Powerlattice to emulate the wide-ranging loads and rapid changes in current demand of next-generation AI accelerators. The demonstration shows how the chiplet responds to these changing demands, highlighting its power delivery and transient response capabilities.

About Powerlattice

Powerlattice is reimagining power delivery for next-generation AI accelerators with the industry’s first power delivery chiplet. Powerlattice tightly integrates power and compute, delivering power precisely where and when it’s needed to achieve the breakthrough performance, efficiency and reliability that next-generation AI and data center infrastructure demands. The company is headquartered in Vancouver, WA, with additional offices in Chandler, AZ and San Jose, CA.

Media contact
Elly Akopyan
powerlattice@voxuspr.com

View source version on businesswire.com: https://www.businesswire.com/news/home/20261026645729/en/