Next-generation system-level design platform integrates Forte and Cadence technology HIGHLIGHTS: - Industry's first high-level synthesis platform that can be utilized across an entire system-on-chip (SoC) design
- First silicon-proven high-level synthesis platform to address real world challenges, including ECO, low power, IP reuse, and routing congestion - Consistent environment from TLM through gates improves design and verification quality SAN JOSE, Calif.
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