2013/2/13 - Multi-output, 1.65-GHz Clock Buffer and Divider Delivers Low Jitter to Optimize Noise Performance in Ultra-high-speed Data Converters

• View product page, download data sheet and order samples: http://www.analog.com/en/clock-and-timing/clock-generation-and-distribution/ad9508/products/product.html
• Learn more about ADI’s clock generation and distribution technology: http://www.analog.com/en/clock-and-timing/clock-generation-and-distribution/products/index.html
• View discussions on clocking and timing on EngineerZone™, an online technical support community: http://ez.analog.com/community/clock_and_timing

AD9508 1.65 GHz Clock Buffer and Divider Key Features

• RMS jitter in HSTL output mode:
  
  
  • 41 fs @ 622.08 MHz (12 kHz to 20 MHz)
  • 72 fs @ 622.08 MHZ (20 kHz to 80 MHz)
• Dividers are pin-strappable for division factors of 1,2,4,8, or 16
• Outputs: 4 LVDS or HSTL; 8 single-ended CMOS
• Output-to-output skew: <48 ps (LVDS)
• Supply voltage: 2.5 V/3.3 V

Availability, Pricing and Complementary Components

The AD9508 Clock buffer/divider complements ADI’s clock generator and high-speed data converter portfolio.

About Analog Devices

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